The present invention relates to the field of programmable integrated circuits and in particular, to decoder circuitry for an embedded memory of a programmable logic device.
Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Many programmable logic integrated circuits also included embedded user-programmable memory or RAM.
There is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. One of the critical speed paths of the programmable logic integrated circuit is the read and write paths of the memory. It is desirable that reading and writing of the memory is a high-speed path. A memory address is decoded to access the appropriate located in the embedded memory. The address decoding delay is part of the read and write delay in access the memory.
Therefore, there is a need to provide high performance address decoding techniques and circuitry in order to improve the performance of the integrated circuit.